module bus (
input clk,
input rst_n,
input ava_wr_n,
input ava_rd_n,
input [15:0] ava_addr,
input [31:0] ava_data_out,
output [31:0] ava_data_in,

output wr_n,
output rd_n,
output [15:0] addr,
output [31:0] data_out,
input  [31:0] data_in
);

assign wr_n=ava_wr_n;
assign rd_n=ava_rd_n;
assign addr=ava_addr;
assign data_out=ava_data_out;
assign ava_data_in=data_in;
endmodule 
